1. Related Applications
The present invention is related to our U.S. application Ser. No. 07/138,183 filed Dec. 28, 1987, now U.S. Pat. No. 4,870,660 for a Variable Frequency Rate Receiver and to our U.S. application Ser. No. 07/222,700 filed July 22, 1988, now U.S. Pat. No. 4,889,042 for "A High-Speed Multi-Channel Phase Detector".
2. Field of the Invention
The present invention is related to bit synchronizers of the type employed in high-speed devices such as multi-phase shifted key (PSK) receivers. More particularly, the present invention relates to a high-speed bit synchronizer for generating a clock and data output which is synchronized to the input data stream.
3. Description of the Prior Art
Prior art bit synchronizers may be implemented as early-and-late gate bit synchronizers or as delay and multiply and/or by implementing a digital transition tracker. One of these sample and hold early-and-late gate bit synchronizers will be explained with the drawings of the prior art herein. Sample and hold bit synchronizers are analog devices which are both expensive and are relatively slow speed devices that are limited to about 60 megacycles before incurring distortion and excessive jitter. Sample and hold circuits are commercially available as hybrid devices which are relatively large and consume a large amount of power when driven at high speeds. It is difficult to incorporate such devices into miniaturized bit synchronizers. Such sample and hold synchronizers are not capable of high-speed operation. A typical Burr-Brown part SHC 6000BH is rated at 60 megacycles at one percent distortion level and distortion would increase at higher rates. Accordingly, it would be desirable to provide a bit synchronizer which is both faster and cheaper than bit synchronizers heretofore provided in the prior art.